This invention relates generally to analog-to-digital converters (ADC), and more specifically to wave-pipelined ADCs.
There are many analog-to-digital signal conversion (ADC) methods and apparatus. One of the well known ADC methods and apparatus is an synchronous pipeline ADC with error correction.
Reference is now made to FIG. 1A, a block diagram of prior art error correction synchronous pipeline ADC architecture 1. Reference is made in parallel to FIG. 1B, a block diagram of a prior art sample stage 10. ADC 1 may comprise a series of stages 10. Each stage 10 may typically comprise one or more sub-stages, such as a sample/hold (SH) circuit 12, ADC 14, digital to analog converter (DAC) 16, substractor 17 and amplifier 18. As is commonly known in the art, the signal flow within and between stages 10 is regulated via synchronized strobes or clock signals. In FIGS. 1A and 1B, each progressive strobe or clock signal is represented by a xe2x80x9cclkxe2x80x9d, i.e. clk1, clk2, etc.
FIG. 1B also illustrates an exemplary flow of a analog-to-digital conversion in exemplary stage 10. An analog signal 22 is received by SH 12, which samples and holds a sample analog value 24. Upon clk1, SH 12 transfers sample 24 to ADC 14 and to substractor 17. ADC 14 converts sample 24 to a digital signal 26 representative of the sample 24. Upon clk2, ADC 14 transfers digital signal 26 to a register or latch (not shown) and to DAC 16. DAC 16 receives digital signal 26 and converts it to a reconstructed analog signal 28, representative of a quantization of sample 24. Upon clk 3, DAC 16 transmits reconstructed signal 28 to substractor 17. Substractor 17 first calculates the quantization error between sample 24 and reconstructed signal 28. Subtractor 17 then transmits the result to amplifier 18. Upon clk 4, amplifier 18 transmits multiplied signal 30 to the next stage 10. Upon the next clk (not shown) the present cycle is repeated. Each stage 10, and the elements comprised therein, progress synchronously with each other stage 10.
It is noted that the above sample is a typical known in the art routine. As an example, ADC 14 is illustrated as 1.5 bit ADC, however, may be a single bit ADC or any other known in the art ADC. Stage 10 may have various alternative elements or may proceed upon alternative paths, however, the basic principle is similar to that presented in such that the entire process is regulated via synchronized clock strobes.
A disadvantage of the above procedure is that a comparator or stage may not complete its function during the clocked period, and may hence transmit a partial, incomplete or incorrect signal. Other drawbacks are the need for dedicated complex clocking circuits, the vulnerability to clock jitter and process variations, and a non-scalable power budget.
In accordance with one aspect of the present invention, there is now provided an apparatus and method of analog-to-digital conversion, wherein the elements and stages in an analog-to-digital (AD) wave pipeline architecture are not regulated via a synchronized clock. Rather, upon completion of each stage or function, the relevant element or stage transmits a xe2x80x9ccompletedxe2x80x9d signal, or an xe2x80x9cACKxe2x80x9d signal to the next element/stage. The xe2x80x9cACKxe2x80x9d signal then triggers that element/stage. Each stage thus receives the time necessary for proper operation, in a manner that is independent of the sampling frequency. Due to the novel xe2x80x9cACKxe2x80x9d triggering method, the present invention is robust to technology scatter, process variations, and jitter problems. This robustness is in contrast to prior art circuits wherein each element and stage is allotted a predefined clocked period, which alternatively may be too much or too little time.
Another advantage of the present invention may be the elimination of global clocks in or between the stages. Inasmuch as no global clocks are needed, the design complexity may be reduced and the risk may be lowered.
In some preferred embodiment, each stage may be powered up only when it is required to process its input data. Furthermore, all stages may be powered down upon completion of the analog-to-digital converstion process. Thus, another advantage of the present invention may be scalable power consumption via application of a lower clock frequency, resulting in a reduced average power consumption.
In accordance with one aspect of the present invention, there is now provided a method for converting a signal from analog-to-digital domain. Upon receipt of an ith triggering signal, where 1xe2x89xa6ixe2x89xa6N, the method includes initiating at least a partial AD operation. Upon completion of the at least partial operation, the method may includes generating and transmitting an ith+1 triggering signal. The ith+1 triggering signal may be adapted to initiate an ith+1 at least partial operation, thereby creating an asynchronous process. The method further includes repeating the above operations until completion of the analog to digital conversion. In some embodiments of the present invention, upon completion of the conversion, i=N and the ith+1 operation is a power-down function.
In accordance with one aspect of the present invention, there is now provided ananalog-to-digital (AD) wave pipeline system. The system may include a plurality of AD pipeline stages in series, each of the stages, upon receipt of an ith triggering signal where 1xe2x89xa6ixe2x89xa6N, may intiate an AD operation. Upon completion of the operation, each stage may generate and transmit an ith+1th triggering signal adapted to initiate an ith+1 operation, thereby creating an asynchronous process.
In accordance with one aspect of the present invention, there is now provided an analog-to-digital (AD) stage. The stage may include a plurality of sub-stages, each sub-stage, upon receipt of an ith triggering signal where 1xe2x89xa6ixe2x89xa6N, may intiate a partial AD operation. Upon completion of the partial AD operation, each sub-stage may generate and transmit an ith+1 triggering signal adapted to initiate an ith+1 partial AD operation, thereby creating an asynchronous process. Each sub-stage may include a shut down mechanism adapted to shut down the sub-stage when i=N and upon receipt of the ith+1 triggering signal.